The present invention relates to a compound semiconductor field effect transistor and a method of forming the same, and more particularly to a group III-V compound semiconductor hetero-junction field effect transistor.
The group III-V compound semiconductor hetero-junction field effect transistor is a high speed and high frequency device which is superior in low noise, high output and high efficiency. The typical group III-V compound semiconductor is, for example, GaAs based compound semiconductor and InP-based compound semiconductor. A high electron mobility transistor and a p-n junction field effect transistor are the typical compound semiconductor hetero-junction field effect transistors. An ON-resistance is a total resistance between a source electrode and a drain electrode through a channel layer or an active region. The possible reduction in contact resistance is important for obtaining high output and high efficiency in low voltage driving condition.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a first conventional hetero-junction field effect transistor. The first conventional hetero-junction field effect transistor has the following structure. An AlGaAs buffer layer 203 is provided on a top surface of a semi-insulating GaAs substrate 201. An undoped InGaAs layer 204 is provided on a top surface of the AlGaAs buffer layer 203. An n-AlGaAs layer 205 is provided on a top surface of the undoped InGaAs layer 204. A pair of n+-GaAs ohmic contact layers 202 are selectively provided on a top surface of the n-AlGaAs layer 205. The n+-GaAs ohmic contact layers 202 may be formed by forming a single n+-GaAs ohmic contact layer on a top surface of the n-AlGaAs layer 205 and then selectively etching the single n+-GaAs ohmic contact layer to form, a recessed portion in the n+-GaAs ohmic contact layer, thereby to form the n+-GaAs ohmic contact layers 202, wherein a part of the top surface of the n-AlGaAs layer 205 is shown under the recessed portion. A gate electrode 208 is selectively provided on the shown part of the top surface of the n-AlGaAs layer 205, wherein the gate electrode 208 is distanced from the n+-GaAs ohmic contact layers 202. Source and drain electrodes 206 and 207 are respectively provided on the top surfaces of the n+-GaAs ohmic contact layers 202. The three laminated layers, for example, the n+-GaAs ohmic contact layers 202, the n-AlGaAs layer 205 and the undoped InGaAs layer 204 provide potential barriers to electron currents between the source and drain electrodes 206 and 207 and a two-dimensional electron gas layer formed in the undoped InGaAs layer 204. Those potential barriers increase the contact resistance.
In Japanese laid-open patent publication No. 5-175245, it is disclosed that in order to reduce the contact resistance or reduce the potential barrier, n+-GaAs ohmic contact layers are selectively provided on parts of a top surface of a semi-insulating GaAs substrate and source and drain electrodes are respectively provided on top surfaces of the n+-GaAs ohmic contact layers, and a multi-layer structure is also selectively provided on the top surface of the semi-insulating GaAs substrate and the multi-layer structure is sandwiched between the n+-GaAs ohmic contact layers. FIG. 2 is a fragmentary cross sectional elevation view illustrative of a second conventional hetero-junction field effect transistor. The second conventional hetero-junction field effect transistor has the following structure. An AlGaAs buffer layer 303 is selectively provided on a part of a top surface of a semi-insulating GaAs substrate 301. An undoped InGaAs layer 304 is provided on a top surface of the AlGaAs buffer layer 303. An n-AlGaAs layer 305 is provided on a top surface of the undoped InGaAs layer 304. The laminations of the AlGaAs buffer layer 303, the undoped InGaAs layer 304 and the n-AlGaAs layer 305 form a multi-layer structure. A first n+-GaAs ohmic contact layer 302-1 is selectively provided on the top surface of the semi-insulating GaAs substrate 301 and the first n+GaAs ohmic contact layer 302-1 is adjacent to and in contact with a first side face of the multi-layer structure. A top level of the first n+-GaAs ohmic contact layer 302-1 is higher than the top surface of the multi-layer structure. A second n+-GaAs ohmic contact layer 302-2 is selectively provided on the top surface of the semi-insulating GaAs substrate 301 and the second n+-GaAs ohmic contact layer 302-2 is adjacent to and in contact with a second side face of the multi-layer structure, wherein the second side face of the multi-layer structure is positioned in opposite side to the first side face of the multi-layer structure. A top level of the second n+-GaAs ohmic contact layer 302-2 is higher than the top surface of the multi-layer structure. The multi-layer structure is sandwiched between the first and second n+-GaAs ohmic contact layers 302-1 and 302-2. A source electrode 306 is provided on the first n+-GaAs ohmic contact layer 302-1. A drain electrode 307 is provided on the second n+-GaAs ohmic contact layer 302-2. A gate electrode 308 is selectively provided on a part of a top surface of the n-AlGaAs layer 305, so that the gate electrode 308 is distanced from the first and second n+-GaAs ohmic contact layers 302-1 and 302-2 and also from the source and drain electrodes 306 and 307. Only the first and second n+-GaAs ohmic contact layers 302-1 and 302-2 provide potential barriers to electron currents between the source and drain electrodes 306 and 307 and a two-dimensional electron gas layer formed in the undoped InGaAs layer 304. The n-AlGaAs layer 305 and the undoped InGaAs layer 304 provide no potential barriers to the electron currents. Those potential barrier, to which the electron currents sense, is lower than that of the first conventional structure of FIG. 1. The lower potential barrier results in a lower contact resistance. The current path is defined by a contact area between a channel layer and the first and second n+-GaAs ohmic contact layers 302-1 and 302-2. Namely, the contact area between a channel layer and the first and second n+-Gas ohmic contact layers 302-1 and 302-2 depends upon a thickness of the channel layer. The channel layer is, however, thin. In case of the high electron mobility field effect transistor, the thickness of the channel layer is approximately 15 nanometers. It is difficult for the advanced compound semiconductor hetero-junction field effect transistor to increase the thickness of the channel layer.
The above second conventional structure of the ohmic contact layers 302 may be formed by either one of the following three methods. The first conventional fabrication method is that the above multi-layer structure is epitaxially grown for subsequent selective ion-implantation into source and drain regions in the multi-layer structure. The second conventional fabrication method is that a single ohmic contact layer having a high impurity concentration is formed for subsequent selective etching process to form a recessed portion, whereby the single ohmic contact layer is divided into two parts, before the multi-layer structure having the channel layer is then formed in the recessed portion, so that the multi-layer structure is interposed between the two ohmic contact layers. This second conventional method is disclosed in the above Japanese laid-open patent publication No. 5-175245. The third conventional fabrication method is that the multilayer structure having the channel layer is epitaxially grown for subsequent selective etching to the multilayer structure in source and drain regions before ohmic contact layers are selectively formed on the source and drain regions so that the multi-layer structure is sandwiched between the ohmic contact layers.
As long as it is difficult to reduce the thickness of the channel layer in the advanced compound semiconductor field effect transistor, it is difficult to further reduce the contact resistance from the electrodes to the channel layer.
In the above circumstances, it had been required to develop a novel field effect transistor and method of forming the same free from the above problem.
Accordingly, it is an object of the present invention to provide a novel ohmic contact layer structure in a compound semiconductor device free from the above problems.
It is a further object of the present invention to provide a novel ohmic contact layer structure in a compound semiconductor device, wherein a contact resistance from electrode to a channel layer is reduced.
It is a still further object of the present invention to provide a novel compound semiconductor field effect transistor free from the above problems.
It is yet a further object of the present invention to provide a novel compound semiconductor field effect transistor reduced in a contact resistance from electrode to a channel layer.
It is a still further object of the present invention to provide a novel method of forming a compound semiconductor field effect transistor free from the above problems.
It is yet a further object of the present invention to provide a novel method of forming a compound semiconductor field effect transistor reduced in a contact resistance from electrode to a channel layer
The first present invention provides a structure of a semiconductor device, the structure comprising a compound semiconductor multi-layer structure having at least a channel region; and at least an ohmic contact layer provided adjacent to a first side face of the multi-layer structure, and the ohmic contact layer being in contact with at least a part of the first side face, wherein the ohmic contact layer has a top extending portion which extends in contact with a part of a top surface of the multi-layer structure.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.